Shadow Receive Buffer Register (n)
| SRBRN | This is a shadow field for the UART_RBR[RBR] field and has been allocated 16 32-bit locations so as to accommodate burst accesses from the master. This field contains the data byte received on the UART_RX in UART mode. The data in this field is valid only if the UART_LSR[DR] bit is set. If FIFOs are disabled (UART_FCR[FIFOE] set to 0), the data in the UART_RBR[RBR] must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (UART_FCR[FIFOE] set to 1), this register accesses the head of the Rx FIFO. If the Rx FIFO is full and this field is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. |